The subject application is related to subject matter disclosed in the Japanese Patent Application No.Hei12-30948 filed in Feb. 8, 2000 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
1. Field of the Invention
The present invention is related to an instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit.
2. Prior Art
In the case where a microprocessor is implemented with fixed-length instruction codes (32-bit length in many cases) as RISC processors, the efficiency of coding tends to be low to increase the memory space for storing instruction codes as compared with a microprocessor implemented with variable-length instruction codes (8-bit to 32-bit length in many cases) such as CISC processors. The efficiency of coding used in this description is the ratio of the size of source codes to the size of the corresponding object codes as compiled.
It is difficult to employ such a processor requiring a higher capacity semiconductor memory chip or a number of memory chips for use in personal appliances. Although depending upon the architecture of the RISC processor, there are two main factors of lowering the efficiency of coding as follows.
(a) The length of the instruction codes is long such as the 32-bit fixed length.
(b) There are provided a small number of instructions.
In order to improve the efficiency of coding, with respect to the factor (a), there have been developed RISC processors implemented with fixed-length instruction codes of 16-bit lengths and RISC processors implemented with variable-length instruction codes of 16-bit/32-bit lengths. With respect to the factor (b), there have been developed RISC processors implemented with a variety of instructions comparable to a CISC processor. In the case of the processor with fixed-length instruction codes of 16-bit lengths, the factor (b) is not solved because the number of the available instructions is limited by the shorter bit length of the codes and because the immediate operands as treated are constrained (for example 16-bit data can not directly be manipulated), and therefore the efficiency of coding is not effectively improved. Also, since the number of instructions as required for the same program increases, the performance respective to the operation frequency tends to decrease as compared with a processor implemented with fixed-length 32-bit instruction codes.
RISC processors implemented with variable-length instruction codes of 16-bit/32-bit lengths have been developed to deal with these shortcomings. In this case, high speed operations are implemented with 32-bit instruction codes while the efficiency of coding is improved by providing a mixed sequence of 16-bit instruction codes and 32-bit instruction codes.
The additional instructions to be added to the instruction set of the existing processor include an instruction for switching the instruction mode (the mode in which are executed the original 32-bit instruction codes and the mode in which are executed the additional 16-bit instruction codes or a mixed sequence of 16-bit instruction codes and 32-bit instruction codes), and new instructions which are not corresponding to any 32-bit original instruction codes. For this reason, it is necessary to modify the hardware of the existing processor. For example, the existing processor has to be modified to provide an instruction code expanding circuit for expanding the additional instructions as compressed and an instruction decoding circuit for decoding the new instructions as introduced. Furthermore, it is necessary to modify some circuits inside of the processor such as the pipelined control circuit. The least significant bits of the program counter are used as a register to indicate the current instruction mode. The instruction code expanding circuit and the instruction decoding circuit are controlled with the register.
In the case of the RISC processors implemented with CISC-like complicated instructions, the instruction execution circuit becomes complicated so that it is difficult to enable high speed operations by increasing the operation frequency, which is the general feature of RISC processors. Accordingly, this kind of the processor has been designed to operate only at a relatively low speed (lower than 100 MHz).
On the other hand, several techniques have been proposed in order to improve the efficiency of coding as follows.
A first example is the techniques of generating an instruction code sequence which has a fewer number of steps or shorter code lengths by modifying the compiler or the assembler for generating program codes. Generally, the source text of a target program is described in a high level language such as C-language and so forth. The compiler is used to convert the source text of a target program to an assembly source code program. The assembly source code program is converted into an object program consisting of instruction codes which are directly decoded by a processor. The number of steps is the number of instruction codes. The compiler or the assembler is modified in order that the source text of the target program is converted into a fewer number of instruction codes. On the other hand, in some processor, there are a plurality of the instruction codes having the same function. The assembler is modified in order that the source text of the target programis converted into instruction codes which have shorter code lengths. This function of the assembler is called optimization which can be refined to make shorter the instruction codes.
A second example is the techniques of generating an instruction code sequence which has a fewer number of steps or shorter code lengths by adding new instructions to the processor. There are two cases in accordance with this technique. One is such that a single new instruction is introduced to indicate an operation which is accomplished by a plurality of existing instructions. The other is such that a new instruction is introduced to indicate an original instruction with a shorter code.
A third example is a modification of the second example. In accordance with the third example, additional instructions having shorter code lengths are introduced in order that each additional instruction is expanded to an original instruction respectively.
A fourth example is the techniques of generating an instruction code sequence which has a fewer number of steps or shorter code lengths by replacing original instructions of the processor by new instructions.
A fifth example is the techniques of compressing the entirety or part of a program composed of native instructions of the processor by a software and, when executed, the program as compressed is expanded by a software or a hardware. In accordance with the fifth example, it is possible to reduce the program memory as required in advance of execution on the basis of the ZIP algorithm, the LZH algorithm and so forth in the same manner as a file is compressed and expanded.
A sixth example is a modification of the fifth example. In accordance with the sixth example, a program composed of native instructions of the processor is divided into a plurality of blocks. Compression and expansion is performed for each block. The program as compressed is executed while expanding each block by a software or a hardware.
The technique in accordance with the first example has shortcomings that the limitation of the original instruction codes of the processor can not be overcome so that the efficiency of coding is improved only to the extent that the native instruction codes of the processor are effectively utilized. When further improvement becomes necessary, any of the second to sixth examples has to be employed. The technique in accordance with any of the second to fourth examples means that a new processor has to be developed and therefore it takes much development time and resources to develop a software development environment, i.e., language tools such as a compiler and an assembler, test tools such as an ICE/Debugger, an OS, Co-simulation tools and so forth. Particularly, in the case of a general purpose computer, different users have different software development environments in general so that a plurality of software development supporting tool sets have to be prepared incurring substantial additional costs.
The technique in accordance with the third example also requires modification the existing processor in order that, while the additional instructions have shorter code lengths, the addresses given to the program memory for fetching the additional instructions are coincident to the corresponding addresses of the processor. For example, in the case where the original instructions are composed of 32-bit fixed-length instruction codes while the additional instructions are composed of 16-bit fixed-length instruction codes as illustrated in FIG. 1, each 32-bit original instruction occupies 4 bytes of the memory space while each 16-bit original instruction occupies 2 bytes of the memory space. The addresses for fetching the additional instructions have to be multiples of 2. Because of this, the processor is modified in order to increment by two the instruction address as treated in the processor. Furthermore, there has to be implemented an additional instruction for selecting either the additional instruction set or the original instruction set. In accordance with the third example, it also takes much development time and resources to develop a software development environment and tools. Even though the third example tends to lessen the burden as compared with the second example, the development is not so easy.
In accordance with the fifth example, it is possible to achieve a high compression rate since compression can be performed inclusive of data (the actual compression rate is depending upon the program). However, it takes a substantial time to expand compressed instructions and data, which require an extra memory space for loading the expanded instructions and data in addition to the compressed instructions and data. The application thereof is limited to some appropriate fields. Particularly, in the case where the compressed instructions are expanded by a software, the program can not be executed until expansion which takes much time. Even if the compressed instructions are expanded by hardware control, the memory has to be accessed to the compressed instructions and therefore the performance penalty is substantial.
In accordance with the sixth example, since the program composed of native instructions is divided into a plurality of blocks. Compression and expansion is performed for each block. The expansion of the compressed instructions takes a processing time which is depending on the size of the respective blocks but substantially improved as compared with the fifth example. Also, after the compression, the respective blocks of the program have different sizes so that it is necessary to save the correspondence information of the processor addresses and the memory addresses for expanding the compressed instructions. Namely, the compressed instructions are expanded by preparing in the program memory in advance an index table for obtaining the addresses of the compressed instructions from the processor address, reading the index table from the program memory, obtaining the addresses of the compressed instructions from the index table, reading a decoding lookup table which provides information about the compression and has been prepared in a memory region other than the program memory in advance, and expanding the compressed instructions with reference to the decoding lookup table. The expansion process therefore requires much time while the provision of the decoding lookup table tends to increase the chip cost.
Meanwhile, in a conventional information processing system, the improvement of performance is possible by the use of a wider bus for communication between the processor and the program memory in order to increase the number of instructions fetched per bus cycle. However, if a wider bus is used, a larger number of pins have to be provided for packages of the processor and the program memory which may possibly be composed of a plurality of memory chips while the area required of the circuit board is increased as the bus width is increased. On the other hand, if the bus width is simply reduced, one instruction can not be fetched in one bus cycle resulting in the performance penalty. If the 16-bit instruction codes are employed, a 16-bit bus is used to make it possible to fetch each instruction in each bus cycle and decrease the costs and the size without compromising the performance.
As explained above, in the case of some of the above described conventional techniques, 16-bit fixed instruction codes or the 16-bit/32-bit variable instruction codes are introduced by developing a processor anew or by substantially modifying the existing target processor. For this reason, much time and labours are inevitable for modifying the processor and development of software development tools. Furthermore, in accordance with some of the above described conventional techniques, the compressed instruction are used for improving the efficiency of coding without modifying the processor. However, expansion of the compressed instructions takes much time and necessitates the increase in the size and the costs of the system.
The present invention has been made in order to solve the shortcomings as described heretofore. It is an object of the present invention to provide an instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit, in order to improve the efficiency of coding of the program and reduce the program memory as required for storing the program by making use of an existing processor as selected without modification.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved information processing system comprising: a processor capable of executing native instruction codes; a program memory for storing a program at least part of which comprises compressed instruction codes; an instruction code conversion unit connected to said processor and said program memory for receiving an address of a native instruction code as outputted from said processor, converting the address of said native instruction code to the address of a corresponding native instruction code in said program memory, reading out said compressed instruction codes from the address of said compressed instruction code as converted, converting said compressed instruction code to said native instruction code as converted, and transferring said native instruction to said processor, wherein said instruction code conversion unit performs conversion of the address of said native instruction code to the address of the corresponding compressed instruction code in said program memory by shifting the address of said native instruction code as outputted from said processor to the right by one bit.
In a preferred embodiment, further improvement resides in that said instruction code conversion unit accesses to said program memory through a memory interface.
In a preferred embodiment, further improvement resides in that said compressed instruction codes are m-bit fixed-length codes or m-bit/n-bit (nxe2x89xa7m) variable-length codes while said native instruction codes are n-bit fixed-length codes.
In a preferred embodiment, further improvement resides in that said program memory includes a compressed instruction code address range for storing said compressed instruction codes and a native instruction code address range for storing said native instruction codes while the addresses of the native instruction codes as outputted from said processor are used as means for distinguishing between said compressed instruction codes and said native instruction codes.
In a preferred embodiments further improvement resides in that said compressed instruction codes are variable-length codes; and wherein said program as stored in said program memory is divided into a plurality of memory blocks of said compressed instruction codes in order that the leading bits of each memory block are occupied by high order bits of a compressed instruction code.
In a preferred embodiment, further improvement resides in that said instruction code conversion unit is provided with a buffer memory for storing the native instruction codes as converted by said instruction code conversion unit.
In a preferred embodiment, further improvement resides in that said buffer memory is composed of a plurality of buffer memory blocks each of which accommodates native instruction codes corresponding to said compressed instruction codes with which one memory blocks is filled; and wherein each buffer memory block is provided with a block address storing register for storing information indicative of the addresses of the native instruction codes stored therein.
In a preferred embodiment, further improvement resides in that said information processing system is provided with a comparator circuit for comparing the addresses of the native instruction codes as stored in said buffer memory blocks with the address of the native instruction code as outputted from said processor.
In a preferred embodiment, further improvement resides in that said information processing system is provided with a register indicative of whether or not the information stored in said block address storing register is valid.
In accordance with another aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved instruction code conversion unit connected to a processor capable of executing native instruction codes and a program memory for storing a program at least part of which comprises compressed instruction codes, receiving an address of a native instruction code as outputted from said processor, converting the address of said native instruction code to the address of a corresponding native instruction code in said program memory, reading out said compressed instruction codes from the address of said compressed instruction code as converted as converted, converting said compressed instruction code to said native instruction code as converted, and transferring said native instruction to said processor, wherein said instruction code conversion unit performs conversion of the address of said native instruction code to the address of the corresponding compressed instruction code in said program memory by shifting the address of said native instruction code as outputted from said processor to the right by one bit.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved instruction code generation method for the information processing system, said method comprising: a step of assembling a source program with said subset of said native instruction codes in order to generate an assembler source program; a step of converting said assembler source program to a relocatable object; a step of converting said relocatable object to an absolute object file consisting of said native instruction codes; a step of converting said absolute object file consisting of said native instruction codes to an absolute object file consisting of said compressed instruction codes by shifting addresses of said native instruction codes written in said absolute object file consisting of said native instruction codes by one bit to the right and converting said native instruction codes to said compressed instruction codes; and a step of converting said absolute object file consisting of said compressed instruction codes to an object program loadable to said program memory.